One common interface used in computer systems is Peripheral Component Interconnect (PCI) Express (“PCIe”, in accordance with PCI Express Base Specification 3.0, Revision 0.5, August 2008). PCIe specification defines several Active State Power Management (ASPM) mechanism such as L0s, L1, and L2/L3 to allow PCIe controllers to save power when the link is in idle or when the platform is in idle. When a PCIe controller enters ASPM L1 state, power gating may be triggered to reduce leakage power. However, the efficiency of the power gating is directly dependent on the amount of circuitry that is power gated during this period.